1. Field of the Invention
The present invention relates to a semiconductor device, and more specifically, it relates to a semiconductor device having an SOI structure and a method of fabricating the same.
2. Description of the Background Art
FIG. 29 is a plan view showing the structure of a conventional SOI transistor, FIG. 30 is a sectional view along the line 100--100 in FIG. 29, and FIG. 31 is a sectional view along the line 200--200 in FIG. 29. Referring to FIG. 29 to FIG. 31, a buried oxide film 2 is formed on a silicon substrate 1 in the conventional SOI transistor. A silicon layer 3 is formed on the buried oxide film 2. A gate electrode 12 is provided on the silicon layer 3 through a thin gate insulator film 11. A channel region 15 containing a p-type impurity of about 1.times.10.sup.17 /cm.sup.3 is formed in a region of the silicon layer 3 under the gate electrode 12. Source/drain regions 14 containing an n-type impurity of about 1.times.10.sup.20 /cm.sup.3 are formed at a prescribed interval, to hold the channel region 15. Isolation regions 107 containing a p-type impurity of about 1.times.10.sup.18 /cm.sup.3 which is a higher impurity concentration than the channel region 15 are provided on end portions of the silicon layer 3 under the gate electrode 12. These isolation regions 107 are provided for preventing generation of parasitic MOS transistors on the end portions of the silicon layer 3. In more concrete terms, the end portions of the silicon layer 3 are cut off in ordinary mesa shapes or LOCOS (LOCal Oxidation of Silicon)-isolated. The threshold voltages of these end portions lower since electric fields concentrate or the impurity concentration lowers in such end regions, and the so-called parasitic MOS transistors are generated as a result. In general, therefore, the impurity of a higher impurity concentration than the channel forming region 15 is introduced into the end portions of the silicon layer 3 for increasing the threshold voltages of these portions.
An interlayer isolation film 16 is formed to cover the gate electrode 12, and contact holes 17 are formed in the interlayer isolation film 16 on prescribed regions. Aluminum wires 18 are formed to be connected with the gate electrode 12 and the pair of source/drain regions 14 respectively through the contact holes 17.
With reference to FIG. 32 to FIG. 43, a method of fabricating the conventional SOI transistor is now described. First, holding the buried oxide film 2 having a thickness of about 4000 .ANG. on the silicon substrate 1, the silicon layer 3 consisting of a single crystal having a thickness of about 1000 .ANG. is formed thereon, as shown in FIG. 32. The buried oxide film 2 is formed by that high-temperature heat treatment of about 1300.degree. C. is performed after oxygen ions are injected into the silicon substrate 1 at 200 keV by about 2.times.10.sup.18 /cm.sup.2.
Then, a pad oxide film 4 having a thickness of about 300 .ANG. is formed on the silicon layer 3, and a silicon nitride film 5 having a thickness of about 2000 .ANG. is formed thereon, as shown in FIG. 33. A photoresist 6 shown in FIG. 34 is formed in a prescribed region on the silicon nitride film 5 with a photolithographic technique. This photoresist 6 has a field active layer pattern. The photoresist 6 is employed as a mask for etching the silicon nitride film 5 and the pad oxide film 4, whereby a silicon nitride film 5 and a pad oxide film 4 of shapes shown in FIG. 35 are formed. Thereafter boron (B) which is a p-type impurity is injected at 20 keV by about 1.times.10.sup.13 /cm.sup.2, whereby the isolation regions 107 shown in FIG. 36 are formed. Thereafter the photoresist 6 is removed.
Then, a silicon nitride film (not shown) is further deposited on the silicon nitride film 5, and thereafter anisotropic etching is performed thereby forming silicon nitride film spacers 10 shown in FIG. 37 on side walls of the silicon nitride film 5. The silicon nitride film 5 and the silicon nitride film spacers 10 are employed as masks for anisotropically etching the silicon layer 3, whereby an island-shaped silicon layer 3 becoming a field active region shown in FIG. 37 is formed. Thereafter the silicon nitride film 5, the silicon nitride film spacers 10 and the pad oxide film 4 are removed so that a shape shown in FIG. 38 is obtained.
Then, the gate electrode 12 shown in FIG. 39 to FIG. 41 is formed to cover an upper surface and both side surfaces of the silicon layer 3 through the gate insulator film 11. FIG. 39 is a sectional view along a direction where the gate electrode 12 extends, FIG. 40 is a sectional view along a direction orthogonal to FIG. 39, and FIG. 41 is a plan view. A channel dope for adjusting the threshold voltage of the transistor, e.g., boron (B) is injected by about 4.times.10.sup.12 /cm.sup.2 before formation of the gate electrode 12, thereby forming the channel forming region 15. The gate electrode 12 is patterned as shown in FIG. 39 to FIG. 41, and thereafter the gate electrode 12 is employed as a mask for injecting arsenic (As) which is an n-type impurity by about 1.times.10.sup.15 /cm.sup.2, as shown in FIG. 42 and FIG. 43. Thus, the n-type source/drain regions 14 holding the channel region 15 are formed. Due to this ion implantation for forming the source/drain regions 14, the isolation regions 107 into which the p-type impurity is introduced in portions other than that under the gate electrode 12 disappear as shown in FIG. 43.
After the aforementioned formation of the source/drain regions 14, the interlayer isolation film 16 is deposited while the contact holes 17 are opened as shown in FIG. 29 to FIG. 31, and thereafter the aluminum wires 18 are formed. Thus, the conventional SOI transistor has been completed.
In the SOI structure formed by working the semiconductor layer 3 in the aforementioned island shape, crystallinity on end surface portions of the silicon layer 3 deteriorates. Therefore, accelerative diffusion of the impurity from the source/drain regions 14 takes place in the end portions of the silicon layer 3 located under the gate electrode 12, and accelerative diffusion regions 105 shown in FIG. 44 are formed. There has been such a problem that, when such accelerative diffusion regions 105 are formed, abnormal leakage characteristics shown in FIG. 45 are caused as transistor characteristics.